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ip_block:liointc

Local I/O Interrupt Controller

This controller can be found in the Loongson-3A and Loongson-2K family of processors as the package interrupt source transforming interrupts from on-chip devices to the CPU core's interrupt line. A controller can manage 32 downstream interrupts, and connect to 4 interrupt pins of 4 cores as upstream.

Variants

There are three known variants of the controller.

VersionChipsNotes
1.03A1000 ~ 3A3000Initial Design
1.0a3A4000Bug Fix + CSR ISR
2.02K1000Auto Bounce

Registers

Main Registers

Most registers are bit hot, which means a bit controls an interrupt.

NameOffsetSizeAttributeAviliabilityDescription
INT_ROUTE0x00x20R/WAllRoute config per interrupt, a byte for a interrupt
ISR0x200x4ROAllInterrupt status (1 for pending)
IEN0x240x4ROAllInterrupt enabled (1 for enabled)
IEN_SET0x280x4WOAllEnable interrupt (write 1 for set)
IEN_CLR0x2c0x4WOAllClear and Disable interrupt (write 1 for clear)
INT_POL0x300x4R/WAll?Interrupt trigger polarity (1 for high, 0 for low)
INT_EDGE0x340x4R/WAll?Interrupt trigger type (1 for edge, 0 for level)
INT_BOUNCE0x380x4R/W2.0Interrupt Bounce Config
INT_AUTO0x3c0x4R/W2.0Interrupt Auto Config

per-core ISRs

ISR for every core appears to be different on different chips. For 3A4000 there is even a CSR register to read local ISR. Please check the chip's page.

Functions

Route

Every downstream interrupt can be routed to a core's interrupt line via INT_ROUTE register. For a single downstream interrupt, it's one-byte route config register contains two parts, target core, and target pin.

bit7:40:3
Pin (Each bit for a pin)Core (Each bit for a core)

Pin 0~3 means IP2~5 of MIPS core.

Note that only one pin in one core as the target is allowed for a downstream interrupt.

Auto Bounce

W.I.P.

Errata

LPC Suprious

Interrupts triggered by LPC (INT 10) sometimes missing in the ISR register. If the upstream core receives an interrupt but failed to read anything from ISR than it should come from LPC.

It has been fixed in version 1.0a.

Junk ISR

In version 2.0, ISR sometimes contains junk. Please read per-core ISR instead of the main ISR.

ip_block/liointc.txt · 最后更改: 2021/02/05 04:26 由 windows1089